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22 A Molisch, Status of models for UWB propagation channels, IEEE 802 Interim Meeting, IEEE P80215-04/195r0, Orlando, FL, March 2004 23 J Kunisch and J Pamp, Measurement results and modeling aspects for the UWB radio channel, Proc IEEE Conf on UWB Systems and Technologies, pp 19 23, Baltimore, MD, May 2002 24 Z Sahinoglu and A Catovic, A hybrid location estimation scheme (H-LES) for partially synchronized wireless sensor networks, Proc IEEE International Conf on Communications (ICC 04), Paris, June 2004 25 A Catovic and Z Sahinoglu, The Cramer Rao bounds of hybrid TOA/RSS and TDOA/RSS location estimation schemes, IEEE Communications Letters, vol 8, no 10, pp 626 628, October 2004 26 J-Y Lee and R A Scholtz, Ranging in a dense multipath environment using an UWB radio link, IEEE Transactions on Selected Areas in Communications, vol 20, no 9, pp 1677 1683, December 2002 27 J C.



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Adams, W Gregorwich, L Capots, and D Liccardo, Ultra-wideband for navigation and communications, Proc IEEE Aerospace Conf, vol 2, pp 785 792, Big Sky, MT, March 2001 28 H V Poor, An Introduction to Signal Detection and Estimation, Springer-Verlag, New York, 1994 29 C E Cook and M Bernfeld, Radar Signals: an Introduction to Theory and Applications, Academic Press, New York, 1970 30 Y Shimizu and Y Sanada, Accuracy of relative distance measurement with ultra wideband system, IEEE Conf on Ultra Wideband Systems and Technologies (UWBST 03), Reston, VA, November 2003 31 S Gezici, Z Tian, G B Giannakis, H Kobayashi, A F Molisch, H V Poor, and Z Sahinoglu, Localization via ultra-wideband radios, IEEE Signal Processing Magazine (Special Issue on Signal Processing for Positioning and Navigation with Applications to Communications), vol 22, no 4, pp 70 84, July 2005 32 G L.





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Turin, An introduction to matched lters, IRE Transactions on Information Theory, vol IT-6, no 3, pp 311 329, June 1960 33 M-A Pallas and G Jourdain, Active high resolution time delay estimation for large BT signals, IEEE Transactions on Signal Processing, vol 39, no 4, pp 781 788, April 1991 34 IEEE 80215 WPAN Task Group 3 (TG3) [Online] Available at: wwwieee802org/15/ pub/TG3html 35 I Guvenc and H Arslan, Design and performance analysis of TH sequences for UWB impulse radio, Proc IEEE Wireless Communications and Networking Conf (WCNC 04), vol 2, pp 914 919, Atlanta, GA, March 2004 36 S Gezici, H Kobayashi, H V Poor, and A F Molisch, The trade-off between processing gains of an impulse radio system in the presence of timing jitter, Proc IEEE International Conf on Communications (ICC 2004), vol 6, pp 3596 3600, Paris, June 2004 37 L.

Yang and G B Giannakis, Timing ultra-wideband signals with dirty templates, IEEE Transactions on Communications, submitted 38 M McGuire, K N Plataniotis, and A N Venetsanopoulos, Location of mobile terminals using time measurements and survey points, IEEE Transactions on Vehicular Technology, vol 52, no 4, pp 999 1011, July 2003..

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For UWB systems, accurate timing is very important. Subnanosecond pulses need to be transmitted using an accurate reference clock. Clocking at high speed, however, leads to signi cant power consumption and so must be done sparingly. The choice of the 33 MHz crystal reference clock to drive the UWB transceiver and digital components was based on the desire to keep the overall system clock as low as possible. The higher speed clock is generated only as required for pulse transmission. The use of a DLL coupled with an edge combiner avoids classic frequency synthesis techniques using a PLL and N divider combination. The approach used is presented in Figure 17.6. The high-speed clock used for pulse triggering is generated by taking each edge of the crystal oscillator output and generating a burst of well-controlled, evenly spaced edges that span one period of the crystal oscillator. These evenlyspaced edges are then combined by an AND OR based edge combiner. The phase detector generates UP/DOWN signals according to the phase difference between the reference signal and the nal output stage of the voltage controlled delay line (VCDL). The phase detector architecture was presented in [21]. The DLL is in a locked state if the input and output of the voltage controlled delay line are in phase. One delay cell contains two cascaded CMOS inverters. The delay is adjusted by the charge pump and loop lter through control voltage designed to minimize the phase error. A classi cation of charge pump architectures

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