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where n is the mean number of photons arriving at the receiver during the measurement interval, 0 u t u That is, | 1 (t)|2 is the instantaneous average power of the optical signal for logic 1 By combining the incoming signal with an appropriate local oscillator, one can always transform the amplitude keying with the alphabet of two coherent states A = {|0 0|, | |}, with | = | 1 , to the phase-shift keyed alphabet, 1 2 1 1 , 2 2 1 2 ,



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X 8 SRAM chips (SRAM 0 through SRAM 7) are connected as follows SRAM 0 will be enabled by Pentium BEO# with eight output lines of the SRAM connected to Pentium D7-DO pins, SRAM 1 will be enabled by Pentium BE1# with eight output lines of the SRAM connected to D15-D8 pins, and so on The Pentium will assert BEO# when A2 A1 A0 bits of the address are 000 On the other hand, the Pentium will assert BE1# when A2 A1 A0 bits of the address are 001, and so on Next, consider a read operation such as the Pentium instruction MOV BL,[ 1001HI or a write operation such as the Pentium instruction MOV [ 1001H1,AL Assume (DS) = 3000H The 20-bit physical address is 31001H These values are arbitrarily chosen The Pentium in real mode performs the following steps in Figure 122: 1.





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via the unitary displacement, D 1 = exp( 1 ( a a)) Similarly, if | 0 = |0 , / 2 2 a simple displacement can be used to restore | 0 to the vacuum state

In the case of nonorthogonal quantum states as codewords, the receiver attempts to ascertain which state was transmitted by performing a quantum measurement,

1979 1981

say, , on the channel The operator is described by an appropriate POVM represented by a complete (here countable) set of positive operators [37] resolving the identity, i = I d ,

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The Pentium initiates the cycle by asserting the ADS# pin in T1 (the first clock in the bus cycle) 2 Since A2 A1 A0 = 001 in 31001H, the Pentium outputs LOW on BEl# pin (not shown in the figure), and also outputs upper 17 bits of 3 lOOlH on A19-A3 pins 3 The Pentium outputs a LOW on the W/R# pin for read and outputs a HIGH on the W/R# pin for write 4 For a zero wait-state transfer, the Pentium checks the BRDY# input pin (returned by the external device) in the second clock cycle of the bus cycle BRDY# indicates that the external device has presented valid data on the DATA pins (D 15 -D8 pins in this case since BEl# is asserted) or the external device has accepted data in response to a write.

i v 0 ,

(43)

1989 1991

If the system is not ready to drive or accept data, wait states can be added to these cycles by not returning BRDY# to the Pentium at the end of the secondclock Note that the Pentium will assert BE1# pin since the 20-bit address is 3 lOOlH (not shown in Figure 122) for the byte read or write operation to enable the appropriate memory chip..

where n indexes the possible measurement outcomes We already gave a simple example of a continuous POVM in Section 323 In the same vein, an example of a nite POVM in the Euclidean plane is given by the following cyclotomic polygonal resolution of the unity: 2 n

2 q = I d ,

For binary communication, for which the POVM resolution of the unity reads 0 + 1 = I d , the measurement by the receiver amounts to a decision between two hypotheses: H0 , that the transmitted state is 0 , selected when the measurement outcome corresponds to 0 , and H1 , that the transmitted state is 1 , selected when the measurement outcome corresponds to 1

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Now, possibilities of errors mean that there is some chance that the receiver will select the null hypothesis, H0 (or H1 ), when 1 (or 0 ) is actually present Thus, we have in terms of conditional probabilities p (H0 | 1 ) = tr[ 0 1 ] = tr[(I d 1 ) 1 ] , p (H1 | 0 ) = tr[ 1 0 ] (44)

The total receiver error probability, say, p[ 0 , 1 ], is then given by p[ 0 , 1 ] =

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